The present invention relates to a charge coupled device (hereinafter referred to as "CCD"), and more particularly to a CCD provided with means for automatically setting the bias voltage of the CCD.
In a CCD, electric charge corresponding to an A.C. signal applied to the input electrode of the CCD and electric charge corresponding to a D.C. bias voltage are transferred from an input part to an output part. In order to transfer the electric charge corresponding to the A.C. signal without any distortion, it is required to set the D.C. bias voltage to an appropriate value.
FIG. 1 shows the cross section of an input part of a CCD and an inner potential which appears under each gate electrode at an operation period, and FIG. 2 shows the waveforms of pulse signals for driving a CCD. It is to be noted that the inner potential shown in FIG. 1 is that for an electron and the inner potential for a positive charge becomes high as the distance from the axis of abscissa in a direction toward the lower side of FIG. 1 is larger.
A buried channel CCD having two-layer gate electrodes and driven by a two-phase pulse signal is shown in FIG. 1, by way of example, and an input signal is supplied to the CCD by the diode cutoff method. The structure of the CCD shown in FIG. 1 will first be explained. On a P-type semiconductor substrate 1, there are formed a highly-doped N-type diffusion layer 2, an N-type buried layer 3, and low-doped N-type buried layers 4, 5, 6 and 7 which are produced by doping the N-type buried layer 3 with a P-type impurity. Further, in FIG. 1, reference numerals 8 through 15 designate gate electrodes, and 16 through 19 input terminals each receiving a driving pulse signal.
When a gate voltage is applied to the terminals 17, 18 and 19, the inner potential appearing under the gate electrodes 10, 12 and 14 corresponding to the low-doped buried layers 5, 6 and 7 is higher than the inner potential appearing under the gate electrodes 11, 13 and 15 which do not have such a low-doped buried layer thereunder. For instance, when the inner potential appearing under the gate electrode 10 is compared with the inner potential appearing under the gate electrode 11, the former is higher than the latter. The higher inner potential acts as a potential barrier for a transferred charge, and prevents the charge from flowing backward.
A sampling pulse signal P.sub.S (shown in FIG. 2) is applied to the gate electrode 8 through the terminal 16, and the gate electrode 9 is applied with a D.C. voltage from a constant voltage source 21. A driving pulse signal P.sub.1 (shown in FIG. 2) is applied to the gate electrodes 10 and 11 through the terminal 17, and applied to the gate electrodes 14 and 15 through the terminal 19. Further, a driving pulse signal P.sub.2 (shown in FIG. 2) is applied to the gate electrodes 12 and 13 through the terminal 18. A D.C. bias voltage is supplied from a constant voltage source 20 to the N-type diffusion layer 2 through a resistor 23. A signal which is to be delayed, is supplied from a signal source 22 to the N-type diffusion layer 2 through a coupling capacitor 24.
The output voltages of the constant voltage sources 20 and 21 are well regulated and have appropriate values. Now, let us consider the operation of the input part shown in FIG. 1. At a time t=t.sub.1 the sampling pulse signal P.sub.S takes a high level (as shown in FIG. 2), and a potential well W.sub.8 formed under the gate electrode 8 becomes large in depth. A potential well W.sub.9 formed under the gate electrode 9 and the potential W.sub.8 are filled with electric charge which is supplied from the N-type diffusion layer 2, to the potential V.sub.S1 of the N-type diffusion layer 2. At this time, the driving pulse signal P.sub.1 takes a low level, as shown in FIG. 2. Accordingly, a potential well W.sub.10 formed under the gate electrode 10 is small in depth, and the potential of the well W.sub.10 acts as a potential barrier for the electric charge which is supplied to the potential well W.sub.9. At a time t=t.sub.2, the sampling pulse signal P.sub.S takes a low level, and the potential well W.sub.8 existing under the gate electrode 8 becomes shallow. Thus, the potential well W.sub.9 existing under the gate electrode 9 is separated from the N-type diffusion layer 2, which is the charge supply source. An electric charge Q.sub.in which is stored under the gate electrode 9 at this time, is approximately proportional to a difference between an inner potential .phi..sub.R appearing under the gate electrode 9 and the potential V.sub.S1 of the N-type diffusion layer 2, that is, Q.sub.in =K (.phi..sub.R -V.sub.S1), where K is a constant dependent upon the area of the gate electrode 9, and others.
At a time t=t.sub.3, the driving pulse signal P.sub.1 takes a high level and the driving pulse signal P.sub.2 takes a low level, as shown in FIG. 2. Thus, the electric charge existing under the gate electrode 9 is transferred to a potential well W.sub.11 which is formed under the gate electrode 11. At a time t=t.sub.5, the levels of the driving pulse signals P.sub.1 and P.sub.2 are reversed, and thus the electric charge existing under the gate electrode 11 is transferred to a potential well W.sub.13 which is formed under the gate electrode 13.
Thereafter, each time the levels of the driving pulse signals P.sub.1 and P.sub.2 are reversed, the electric charge is transferred to the next potential well. The above-mentioned potential V.sub.S1 is the sum of the potential V.sub.DC of the constant voltage source 20 and the A.C. signal f(t) from the signal source 22. Accordingly, the electric charge Q.sub.in supplied from the N-type diffusion layer 2 is expressed by the following equation: EQU Q.sub.in =K (.phi..sub.R -V.sub.DC)-Kf(t) (1)
That is, the charge Q.sub.in can be expressed by the sum of the charge Kf(t) proportional to the A.C. signal and the D.C. charge K(.phi..sub.R -V.sub.DC).
Next, the operation of an output part of a CCD will be explained below. FIG. 3 shows the cross section of an output part of a CCD whose output is amplified by using a floating diffusion layer, and shows an inner potential which appears under each gate electrode at an operation period. The structure of the output part shown in FIG. 3 will first be explained. Referring to FIG. 3, an N-type diffusion layer 69 acts as a drain for electric charge transferred from an input part. At a floating diffusion layer 70 of N-type, the electric charge transferred from the input part is converted into a voltage by means of the junction capacitance between the diffusion layer 70 and a P-type substrate 71. Buried layers 72 and 73 are similar to the N-type buried layer 3 shown in FIG. 1, and buried layers 74, 75 and 76 are similar to the low-doped N-type buried layers 4, 5, 6 and 7 shown in FIG. 1. Further, in FIG. 3, reference numerals 77 through 82 designate gate electrodes, and 83 through 85 input terminals each receiving a driving pulse signal. The driving pulse signal P.sub.2 (shown in FIG. 2) is applied to the gate electrodes 77 and 78 through the terminal 83, and the driving pulse signal P.sub.1 (shown in FIG. 2) is applied to the gate electrodes 79 and 80 through the terminal 84. An appropriate D.C. voltage from a constant voltage source 86 is supplied to the gate electrode 81, and a reset pulse signal P.sub.R (shown in FIG. 2) is applied to the gate electrode 82 through the terminal 85. The N-type diffusion layer 69 is connected to a constant voltage source 87, and the floating diffusion layer 70 is connected to a circuit which includes constant current sources 89 and 92, NMOS transistors 88 and 91, a samplehold circuit 90, and an output terminal 93.
Now, let us consider the operation of the output part shown in FIG. 3. At the time t=t.sub.3, the driving pulse signal P.sub.1 takes the high level, and thus a potential well W.sub.80 formed under the gate electrode 80 stores the electric charge transferred from a potential well W.sub.78, which is formed under the gate electrode 78. At this time, the reset pulse signal P.sub.R takes a high level as shown in FIG. 2, and therefore an inner potential appearing under the gate electrode 82 is lowered. Thus, the floating diffusion layer 70 communicates with the diffusion layer 69, and the potential of the floating diffusion layer 70 is made equal to the potential of the diffusion layer 69, that is, a potential determined by the constant voltage source 87. Such an operation is called a reset operation. At a time t=t.sub.4, the reset pulse signal takes a low level, and thus the floating diffusion layer 70 is insulated (or isolated) from the diffusion layer 69. At a time t=t.sub.6, the levels of the driving pulse signals P.sub.1 and P.sub. 2 are reversed, and the electric charge existing under the gate electrode 80 is transferred to the floating diffusion layer 70. When the transferred charge is expressed by Q.sub.S1G and the junction capacitance between the floating diffusion layer 70 and substrate 71 by C, a voltage change .DELTA.V appearing at the floating diffusion layer 70 is given by the following equation: ##EQU1## At a time t=t.sub.7, the levels of the driving pulse signals P.sub.1 and P.sub.2 are again reversed, and thus the next charge is stored in the potential well W.sub.80 which is formed under the gate electrode 80. Thereafter, the operation in a period from t.sub.3 to t.sub.7 is repeated. Accordingly, a voltage waveform appearing at the floating diffusion layer 70 is a comb-shaped waveform having the same period as the driving pulse signals, as shown in FIG. 4A. The reference value E.sub.o of this voltage waveform is made equal to the output voltage of the constant voltage source 87 by the previously-mentioned reset operation. The voltage change .DELTA.V appearing at the floating diffusion layer 70 takes negative values since the transferred charge in the present case is an electron, and the height of the envelope of the voltage waveform is proportional to the signal charge (that is, the electric charge which is injected into the CCD in accordance with the A.C. input signal). In other words, an envelope E.sub.1 shown in FIG. 4A indicates the waveform of the A.C. signal which is to be delayed. The signal shown in FIG. 4A is applied to the sample-hold circuit 90 through a source follower which is made up of the NMOS transistor 88 and constant current source 89. A signal waveform E.sub.2 shown in FIG. 4B is sent from the sample-hold circuit 90 to the output terminal 93 through a source follower which made up of the NMOS transistor 91 and constant current source 92. The output signal from the terminal 93 is sent to a low pass filter (not shown), to remove a high frequency component from the output signal, thereby obtaining a signal waveform E.sub.3 shown in FIG. 4C.
Next, the maximum transferable electric charge will be explained below. Referring to the inner potential distribution at the time t=t.sub.3 (shown in FIG. 1), a potential difference .DELTA..phi..sub.TS between the inner potential appearing under the gate electrode 10 and the inner potential appearing under the gate electrode 11 is determined by the impurity concentration of the N-type buried layer 3 and the impurity concentration of the low-doped N-type buried layers 4, 5, 6 and 7. If electric charge is supplied to the potential well W.sub.11 (which is formed under the gate electrode 11) to such an extent as to exceed the potential difference .DELTA..phi..sub.TS, part of the electric charge will flow back to the potential well W.sub.9 (which is formed under the gate electrode 9) when the inner potential distribution at the time t=t.sub.3 is changed to the inner potential distribution at the time t=t.sub.5 (shown in FIG. 1). Accordingly, the electric charge which can be transferred between potential wells when the levels of the driving pulse signals P.sub.1 and P.sub.2 are reversed, is proportional to the potential difference .DELTA..phi..sub.TS. That is, the maximum transferable electric charge Q.sub.MAX is equal to K.DELTA..phi..sub.TS. Since.ltoreq.0.ltoreq.Q.sub.in Q.sub.MAX, the following formula is obtained: EQU 0.ltoreq.{K(.phi..sub.R -V.sub.DC)-Kf(t)}.ltoreq.K.DELTA..phi..sub.TS (b 2)
When the signal f(t) from the signal source 22 is given by A sin .omega.t, the formula (2) is rewritten as follows: EQU 0.ltoreq.(.phi..sub.R -V.sub.DC -Asin .omega.t).ltoreq..DELTA..phi..sub.TS ( 3)
The maximum amplitude A.sub.MAX of the above signal is obtained when the potential difference (.phi..sub.R -V.sub.DC) is equal to one-half the potential difference .DELTA..phi..sub.TS, that is, when the following equation holds: EQU (.phi..sub.R -V.sub.DC)=1/2.DELTA..phi..sub.TS ( 4)
At this time, the maximum amplitude A.sub.MAX is given by the following equation: EQU A.sub.MAX =1/2.DELTA..phi..sub.TS ( 5)
Accordingly, the output voltages of the constant voltages sources 20 and 21 are selected so as to satisfy the equation (4).
The voltage V.sub.DC is dependent on the constant voltage source 20, and the potential .phi..sub.R is dependent on the constant voltage source 21, the impurity concentration of the N-type buried layer 3, the thickness of an insulating oxide film formed between the gate electrode 9 and the semiconductor substrate, and others. Further, the potential difference .DELTA..phi..sub.TS is dependent on the impurity concentration of the N-type buried layer 3, the impurity concentration of the low-doped N-type diffusion layers 4, 5, 6 and 7, and others. That is, the parameters V.sub.DC, .phi..sub.R and .DELTA..phi..sub.TS vary independently of each other, and therefore the characteristics of CCD vary widely. Accordingly, it is required to adjust the output voltage V.sub.DC of the constant voltage source 20 without fail.
In general, a signal having a sinusoidal waveform and a single frequency is applied to the highly-doped N-type diffusion layer 2, and the voltage V.sub.DC is adjusted so that the harmonic distortion of output is made as small as possible. The voltage V.sub.DC is adjusted manually or automatically by means of a special adjusting tool (method). Thus, the manufacturing cost of CCD is raised. Further, as mentioned above, the parameters V.sub.DC, .phi..sub.R and .DELTA..phi..sub.TS vary independently of each other. Accordingly, it is very difficult to design a temperature compensation circuit for a CCD.